1. Field of the Invention
The present invention relates to phase-locked loop circuits. More particularly, the present invention relates to phase-locked loops having dual reference oscillators.
2. Description of Related Art
As is known in the art, a Phase-Locked Loop (PLL) is a closed-loop circuit that compares the phase of the output signal with the phase of an incoming reference signal. The circuit adjusts itself until the two signals are phase aligned and is thus considered to have the output in phase lock with the input reference signal. Once the loop is locked the phase difference between the output signal and the input signal is very close to zero. The frequency of the output signal is an integer or fractional multiple of the input reference signal's frequency.
Referring to FIG. 1, a phase-locked loop 5 has a stable reference oscillator 10 that provides the incoming reference signal 12 that is compared with the output signal fOUT 35. The output 12 of the reference oscillator 10 is an input to a phase/frequency detector and charge pump circuit 15. The phase/frequency detector and charge pump circuit 15 determines the phase error between the incoming reference signal 12 and the output signal fOUT 35 and provides an output phase error voltage that is an input to the charge pump. The phase error is converted by the charge pump into a correction current that is transferred to the loop filter 20. The loop filter 20 generates a control voltage that varies the frequency of the voltage controlled oscillator 25. The output of the voltage controlled oscillator 25 is the output signal fOUT 35. The output signal fOUT 35 fed in to the feedback divider 30. The feedback divider 30 divides or multiplies the output signal fOUT 35 to create the feedback signal 32 that is compared in the phase/frequency detector and charge pump circuit 15 to generate the correction current. When the phase error has been reduced to zero, the voltage controlled oscillator 25 is not varied and the phase-locked loop 5 is considered locked.
Integrated systems typically have a stable reference oscillator 10 acting as the main system clock. Individual devices within the system use the phase-locked loop 5 to derive their internal clock(s) from the stable master reference oscillator 10. In order to save cost and/or power it is often desirable to use a low-frequency source such as a watch crystal oscillator as the master reference oscillator 10. Using a low-frequency reference imposes a serious limitation on the bandwidth of the phase-locked loop. For an integrated circuit (IC) phase-locked loop 5, this either requires off-chip components or digital filters to achieve a sufficiently low bandwidth.